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C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Product Features
* * * * * * * * * * Supplies: 2 Ref clocks 2 Host (CPU) clocks 1 free running and 5 PCI Clocks 1 48MHz fixed clock 1 48 or 24 MHz fixed clock Separate supply pins for mixed (3.3/2.5V) voltage application. 100 or 66 MHz CPU clock operation -1.5% Spread Spectrum modulation for reducing EMI Rich Power Management Functions. 28-pin SSOP & TSSOP packages for minimum board space.
Frequency Table
SEL 100/66# 0 1 CPU Clock 66.66 MHz 100.00 MHz PCI Clock 33.33 MHz 33.33 MHz
Block Diagram
SEL48#
Pin Configuration
REF2
VDDR
XIN XOUT
OSC SS#
REF1
SEL48#
PLL
48-24M 48-24M/TS#
VDDC
SEL100/66# CS# PD# PS# SS#
PLL
CPU (1,2)
PCI_F
VDDP
VSS XIN XOUT PCI_F PCI1 PCI2 VSS VDDP PCI3 PCI4 PCI5 VDDF 48M 48-24/TS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDR REF/SEL48# REF1/SS# VDDC CPU1 CPU2 VSS VSS PS# VDD CS# PD# SEL100/66# VSS
PCI (1:3)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 1 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Pin Description
PIN No. 2 Pin Name XIN PWR VDD I/O I TYPE XTAL4 Description On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal O-chip reference oscillator output pin. Drives an external parallel resonant crystal (14.318 MHz) when an externally generated reference signal is used. 3.3 volt power supply for core logic. Clock outputs. CPU frequency table specified on page 1. Powers down device when LOW When signal is LOW, stops CPU clocks in low state. Frequency select input pins. See frequency select table on page 1. NO INTERNAL PULLUP RESISTOR IS PROVIDED BY DEVICE 2.5V power for CPU and Host clock outputs. Free running PCI clock 3.3V. Does not stop when PS# is at a logic LOW level PCI output clocks. See frequency table of page 1. When signal is LOW, stops all PCI clocks in low state. 3.3 Volt power supply pins for free running PCI clock output buffer. Fixed 48 MHz clock. Power up selectable 48 or 24 MHz clock. If strapped LOW at powerup causes the devices outputs to be tri-stated until the next power up sequence occurs. At power up this pin determines if the device's spread spectrum modulation feature is enabled or disabled. After power up this pin becomes a reference clock output. A 0 (logic low) enables SSCG and a 1 (logic high) disables SSCG. At power up this pin determine the frequency of the clock at pin 14. If it is LOW, the clock will be 48 MHz, if HIGH the clock will be 24 MHz. After power up this pin will become a reference clock output. Power for fixed clock output buffer. Ground pins for device. Power for Reference Oscillator output buffer.
3
XOUT
VDD
O
XTAL4
19 23, 24 17 18 16
VDD CPU (1,2) PD# CS# SEL100/66#
VDDC -
P O I I I
PWR C100S INP3U INP3U INP3
25 4 5,6,9, 10,11 20 8 13 14
VDDC PCI_F PCI(1:5) PS# VDDP 48M 48-24M/TS#
VDDP VDDP VDDF VDDF
P O O I P O I/O
PWR P100S P100S INP3U PWR U48 U48BU
26
REF1/SS#
VDDR
I/O
U48BU
27
REF2/SEL48 #
VDDR
I/O
U48BU
12 1, 7, 15, 21, 22 28
VDDF VSS VDDR
-
P P P
PWR PWR PWR
Notes 1. INP3U pins have internal pullup resistors that will guarantee to a logic1 (high) level if no connection is made to the device's pin. INP3 pins do not contain this function and must be electrically connected to VDD or VSS by external circuitry to ensure a valid logic 1 or 0 is sensed.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 2 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary
Frequency Selection Table
Descriptions
All Outputs Tri-State 66 MHz 100 MHz Test Mode
48-24M/TS# at Power UP
0 1 1 0
SEL 66/100
0 0 1 1
Outputs CPU PCI
Hi-Z 66.66 MHz 100.00 MHz 7.16 MHz Hi-Z 33.33 MHz 33.33 MHz 2.38 MHz
48M
Hi-Z 48 MHz 48 MHz 7.16 MHz
48/24M
Hi-Z 24/48 MHz 24/48 MHz 7.16/3.58 MHz
Power Management Functions
PS# X 1 0 CS# X 0 1 PD# 0 1 X CPU LOW LOW ON 48M LOW ON ON PCI LOW ON LOW PCI_F LOW ON ON VCOs OFF ON ON
CS# is an input clock synthesizer. It is used to turn off the CPU clocks for low power operation. CS# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock) and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time and CPU clock off latency needs to be 2 or 3 CPU clocks periods in time.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 3 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Power Management Timing
CPU CS#
CPU STOP TIMING
CPU PCI REF 48M PD#
POWER DOWN TIMING
PCI PS#
PCI STOP TIMING
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior to turning off the VCO's and the Crystal. The power-up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. AS# and CS# are considered to be don't cares during the power down operations.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 4 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Power Management Timing Signal
CS# PD#
Signal State
0 (disabled) 1 (enabled) 1 (cold start/normal operation)
Latency No. of rising edges of free running PCI CLOCK (PCIF)
1 1 3 mS
0 (power down) 1 NOTES: 1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable goes low/high to the first valid clock comes out of the device.
Spectrum Spread Clocking
Non -Spread Reduction
Spread
Spectrum Analysis
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 5 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Spectrum Spreading Selection Table
Min (MHz) 98.51285 65.6649 Center (MHz) 99.2634 66.166 Max (MHz) 100.01397 66.667 CPU Frequency 100.00 66.66 % OF FREQUENCY SPREADING 1.5% (-1.5% + 0%) 1.5% (1.5% + 0%) MODE Down Spread Down Spread
Test and Measurement Condition
Out Put Buffer Test Point Specified Test Load Condition CL
Clock Output Wave form
3.3 V Clocking Interface PCI ( 1:5) , 48-24M, REF(1,2) tHKP Duty Cycle 3.3 V 2.4 V 1.5 V 0.4 V 0.0 V tprise tpfall 2.5 V 2.0 V 1.25 V 0.4 V 0.0 V tprise tpfall 2.5 V Clocking Interface CPU (1,2) tHKP Duty Cycle
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 6 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Absolute Maximum Ratings
Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: Maximum Power Supply:
-0.3V 0.3V 0C to + 125C 0C to +70C 7V
This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin should be constrained to the range: VSS<(Vin)DC Parameters
Characteristic Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current (2.5 Volt Supply) Dynamic Supply Current (3.3 Volt Supply) Power Down Mode Power Down Mode Symbol VIL VIH IIL IIH VOL VOH Ioz Idd266 Idd2100 Idd366 Idd3100 I2.5PD I3.3PD Min 2.0 Typ Max 0.8 -66 5 0.4 10 35 45 100 120 200 uA 100 uA Units Vdc Vdc A A Vdc Vdc A mA mA mA mA mA mA Conditions
2.4 -
-
All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) TS# = 1, 100/66 = 0, CS# = 1 TS# = 1, 100/66 = 0, CS# = 1 TS# = 1, 100/66 = 1, CS# = 1 TS# = 1, 100/66 = 1, CS# = 1 PD# at logic low level PD# at logic low level
VDD = VDDF = VDDP=VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 7 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary AC Parameters
Characteristic Output Duty Cycle CPU to PCI Offset Buffer out Skew All CPU and PCI Buffer Outputs Period Adjacent Cycles Period Adjacent Cycles Symbol tOFF tSKEW P P Min 45 1 Typ 50 Max 55 4 250 +250 + 500 Units % ns ps ps pS Conditions CPU and CPU/2 = Measured at 1.25V all others measured at 1.50V CPU = 20 pF load Measured at 1.25V PCI = 30 pF load Measure at 1.50V CPU = 20 pF load Measured at 1.25V PCI = 30 pF Load Measured at 1.5V CPU PCI Only
VDD = VDDF = VDDP =VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C
AC Skew Requirements
Characteristic CPU 48 MHz PCI, PCI_F Ref Bank Skew 175pS n/a 500pS n/a Cycle to Cycle Jitters +/- 250pS +/- 500pS +/- 500pS +/- 500pS VDD 2.5V 3.3V 3.3V 3.3V Skew, Jitters Measure Point 1.25V 1.5V 1.5V 1.5V
Offset Requirements
Characteristic CPU to PCI, PCI-5 Bank Offset 1.5-4.0nS CPU leads Measurement Loads (lumped) CPU @ 20pF, PCI @ 30 pF Measure Points CPU @ 1.25V, PCI @ 1.5V
DC Buffer Characteristics for CPU Outputs
Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol IOHmin IOHmax IOLmin IOLmax TR TF 81 0.4 0.5 Min -82 Typ -67 60 1.6 1.6 Max Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.375 V Vout = 1.2 V Vout = 0.3 V 20 pF Load 20 pF Load
VDD = VDDF = VDDP = VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 8 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary
DC Buffer Characteristics for 48M, 48-24M and REF Outputs
Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol IOHmin IOHmax IOLmin IOLmax TR TF Min -29 29 0.5 0.5 Typ Max -23 27 2.0 2.0 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 20 pF Load 20 pF Load
VDD = VDDP= VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C
DC Buffer Characteristics for PCI_F, PCI (1:5)
Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol IOHmin IOHmax IOLmin IOLmax TR TF Min -33 30 0.5 0.5 Typ Max -33 38 2.0 2.0 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 30 pF Load 30 pF Load
VDDP= VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 9 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Crystal and Reference Oscillator Parameters
Characteristic Frequency Tolerance Mode Pin Capacitance DC Bias Voltage Startup time Load Capacitance Effective Series resistance Power Dissipation Shunt Capacitance X1 and X2 Load Symbol Fo TC TS OM CP VBIAS Ts CL R1 DL CO CL 0.3Vdd Min 12.00 Typ 14.31818 5 Vdd/2 20 -32 0.7Vdd 30 40 0.10 7 Max 16.00 +/-100 +/- 100 pF V S pF Ohms mW pF pF Internal crystal loading capacitors on each pin (to ground) Note 1 Note 1 Units MHz PPM PPM Calibration note 1 Stability (Ta -10 to +60C) note 1 Parallel Resonant Capacitance of XIN and Xout pins Conditions
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 18.0 pF the total parasitic capacitance would therefore be = 20.0 pF(matching CL) Note 1: It is recommended but not mandatory that a crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 10 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary
Package Drawing and Dimensions 28 Pin SSOP Outline Dimensions
INCHES SYMBOL C L E H A A1 A2 B C D D A2 A1 B e A
a
MILLIMETERS MAX 0.078 0.008 0.070 0.015 0.009 0.407 0.212 MIN 1.73 0.05 1.68 0.25 0.13 10.07 5.20 NOM 1.86 0.13 1.73 0.30 0.15 10.20 5.30 0.65 BSC 0.311 8 0.037 7.65 0 0.55 7.80 4 0.75 7.90 8 0.95 MAX 1.99 0.21 1.78 0.38 0.22 10.33 5.38
MIN 0.068 0.002 0.066 0.010 0.005 0.397 0.205
NOM 0.073 0.005 0.068 0.012 0.006 0.402 0.209 0.0256 BSC
E e H a L
0.301 0 0.022
0.307 4 0.030
28 Pin TSSOP Outline Dimensions
INCHES SYMBOL A A1 A2 B C D E e H L a 0.244 0.018 0 MIN 0.002 0.031 0.007 0.004 0.378 0.169 NOM 0.039 0.382 0.173 0.026 BSC 0.252 0.024 0.260 0.030 8 6.20 0.45 0 MAX 0.047 0.006 0.041 0.012 0.008 0.386 0.177 MIN 0.05 0.80 0.19 0.09 9.60 4.30 MILLIMETERS NOM 1.00 9.70 4.40 0.65 BSC 6.40 0.60 6.60 0.75 8 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 11 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Ordering Information
Part Number IMIC9716JY IMIC9716JT Note: Package Type 28 PIN SSOP 28 PIN TSSOP Production Flow Commercial, 0C to +70C Commercial, 0C to +70C
The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. IMI C9716J Date Code, Lot #
Marking: Example:
IMIC9716JY Package Y = SSOP T = TSSOP IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000 Page 12 of 12

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